Adjustable delay element for digital systems

ABSTRACT

An adjustable delay element for digital systems includes a high-pass filter in parallel with a low-pass filter. The high-pass filter passes the higher frequency component of the digital signal and the low-pass filter passes the lower frequency component to introduce a delay into the digital signal. A current multiplier directs a selectable portion of the higher frequency component to aid or oppose the lower frequency component to vary the delay within the signal. An output stage receives the lower frequency component with the selected portion of the higher frequency component and reproduces the digital signal with the delay. Embodiments for both differential and single-ended versions of the corresponding delay element are disclosed.

TECHNICAL FIELD

This invention relates generally to delay elements and more particularlyto an adjustable delay element with improved linear control andincreased adjustment range.

BACKGROUND OF THE INVENTION

One goal in the design of digital systems is to clock data and controlsignals through the system at high clock rates. The higher the clockrate, the faster the these signals move through the system. To achievemaximum system performance, it is necessary to maintain a precise timingrelationship between the clock and data paths. In a latch, for example,the data must be present at the input before the latch is clocked. Adelay element is used to introduce the appropriate delay into the clockpath to produce the desired timing. Often, an adjustable delay elementis preferred to optimize circuit parameters such as set-up or hold timefor a latch or settling time for a digital-to-analog converter.

Prior adjustable delay elements have tended to exhibit a nonlinearresponse to the delay control and a limited adjustment range. Forexample, a delay element commonly used in ECL designs is based uponcontrolling the slew rate of the output emitter followers by adjustingthe standing current in these emitter followers. This method has minimaladjustment range because only the negative-going edges are significantlyaffected by the standing current. In single-ended use, this delayelement is nonsymmetrical, producing variable delay for thenegative-going signals but essentially fixed delay for positive-goingsignals. In differential systems, very slow negative-going edges produceonly small delay changes, and the delay generated is a nonlinearfunction of the control current.

SUMMARY OF THE INVENTION

An object of the invention, therefore, is to provide an adjustable delayelement with improved linear control.

Another object of the invention is to provide such a delay element thattreats positive and negative edges equally, that is, symmetrically.

Another object of the invention is to provide such a delay element withan increased range of delay.

In accordance with the present invention, an adjustable delay elementincludes a low-pass filter means in parallel with a high-pass filtermeans. The low-pass filter means passes the lower frequency component ofthe digital signal, the lower frequency component having a delayrelative to the complete digital signal. The high frequency path passesthe higher frequency component of the signal. A control means directs aselectable portion of the higher frequency component to aid or opposethe lower frequency component to vary the delay within the signal. Anoutput stage then receives the lower frequency component and theselected portion of the higher frequency component and reproduces thedigital signal with the corresponding delay.

Two embodiments of the invention are disclosed. A differential versionutilizes both the in-phase and out-of-phase voltage signals of adifferential input stage. The higher frequency component from eachvoltage signal can be directed in a selectable portion to aid or opposethe lower frequency component. This provides a wide range of delay inthe digital signal. In a single-ended version, only the in-phase outputvoltage is utilized. The range of the delay is more limited but is stilllinearly related to the control currents.

Both of the embodiments provide an adjustable delay element that has asymmetrical delay with respect to the positive-going and negative-goingtransitions of the digital signal.

The foregoing and other objects, features, and advantages of theinvention will become more apparent from the following detaileddescription of preferred embodiments which proceed with reference to theaccompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram of an adjustable delay element in accordancewith the present invention.

FIG. 2 shows a specific embodiment of the delay element of FIG. 1.

FIG. 3 is a timing diagram of signal waveforms within the delay element.

FIG. 4 shows how the voltage signals are compared to produce the delayat the output stage of the delay element.

FIG. 5 shows a single-ended embodiment of the adjustable delay elementof FIG. 1.

FIG. 6 shows how the voltage signal in the single-ended embodiment iscompared to a threshold voltage to produce the delay at the output stageof the delay element.

DETAILED DESCRIPTION

Referring now to FIG. 1 of the drawings, a block diagram of anadjustable delay element according to the invention is shown. A pair ofdifferential voltage signals +V_(IN) and -V_(IN) are present at inputterminals 12 and 14, respectively. The voltage signals +V_(IN) and-V_(IN) represent a digital clock signal and may be the output of ECLgate or other digital logic circuit, as will be further described withrespect to specific embodiments. The voltage signal +V_(IN) is appliedto a node to which a low-pass filter 16 and a high pass filter 18 arecoupled in parallel. The low-pass filter 16 passes the lower frequencycomponent of +V_(IN) along a low frequency path to a summing node A.This lower frequency component has an inherent delay relative to thecomplete voltage signal because the higher frequency component thatprovides the fast transition of the signal has been filtered out. Thehigh-pass filter in turn passes an in-phase higher frequency componentalong a separate, high frequency path. Similarly, the voltage signal-V_(IN), which is of opposite phase to +V_(IN), is applied to a circuitnode to which a low-pass filter 20 and high-pass filter 22 are coupledin parallel. The low-pass filter 20 passes the lower frequency componentof -V_(IN) along a second low frequency path to a summing node B. Thehigh-pass filter 22 in turn passes the in-phase higher frequencycomponent along a second separate high frequency path.

The high frequency paths containing filters 18 and 22 are coupled to acontrol element 24 that may be adjusted to pass selectable portions ofeach higher frequency component to each of the summing nodes A or B asindicated by the internal dashed lines. The control element 24 islinearly responsive to a delay control signal at its input 26 thatdetermines which portion of each higher frequency components is directedto each summing node. Thus, the delay in the digital signal is linearlyrelated to the setting of the control signal.

At one extreme, the control signal may direct the control element 24 tocouple directly the entire portion of each higher frequency component tothe summing node receiving the lower frequency component of the samephase. Such coupling is represented by the parallel dashed lines withinelement 24, with the output of the filter 18 being coupled to summingnode A and the output of filter 22 being coupled to summing node B.Because these higher frequency components are in phase with therespective lower frequency components at the summing nodes, they aid thelower frequency components. This summation at the nodes A and Bsubstantially restores the shape of the original differential voltagesignal (albeit with a slight loss) and removes any delay in itstransmission.

At the other extreme, the control signal may direct control element 24to cross couple each higher frequency component to the summing nodereceiving the lower frequency component of the opposite phase. Suchcoupling is represented by the crossed dashed lines within element 24,with the output of filter 18 being coupled to summing node B and theoutput of filter 22 being coupled to summing node A. These higherfrequency components are out-of-phase with the lower frequencycomponents with which they are summed, thus opposing the lowerfrequencies and further increasing the delay in the voltage signals. Inbetween these extremes exists the range of delay, with selectableportions of each higher frequency component being directed to both nodesA and B to aid or oppose the lower frequency components.

The outputs from summing nodes A and B are coupled to an output stagesuch as comparator 27 for sharpening the level transitions. Thecomparator 24 changes state as one differential voltage exceeds theother and thereby reproduces the digital signal with a delaycorresponding to the delay introduced into the differential voltages.The delay is symmetrical for the positive-going and negative-goingtransitions of the differential voltages and thus has no adverse effecton the reproduced digital signal.

Referring now to FIG. 2 of the drawings, a specific embodiment of thedelay element in FIG. 1 is shown coupled to an emitter-coupled logic(ECL) gate. The ECL gate comprises a pair of opposed transistors Q₁ andQ₂ with their emitters coupled together and to a standing or biascurrent source 28. A terminal 30 on the base of transistor Q₁ receivesthe digital input signal (herein a voltage signal) for comparisonagainst a reference voltage V_(REF) present at a terminal 32 on the baseof transistor Q₂. The reference voltage V_(REF) in an ECL gate istypically set midway between the input signal voltage that produces alogic 1 and the voltage that produces a logic 0. Connected to thecollectors of transistors Q₁ and Q₂ are load resistors R₃ and R₄,respectively, and the supply voltage V_(CC). When the digital signal isa logic 1, for example, the bias current from the current source 28 isdirected through transistor Q₁ which conducts and draws current throughresistor R₁, decreasing the collector voltage of transistor Q₁.Transistor Q₂ is shut off, and its collector voltage rises toward thesupply voltage V_(CC). Conversely, when the input signal is a logic 0,transistor Q₁ is shut off and transistor Q₂ conducts. The output voltageat the collector of transistor Q₂ therefore follows the input voltageand is in-phase with the input, while the output voltage at thecollector of transistor Q₁ is out-of-phase with the input voltage.Coupled to the outputs of the ECL gate as emitter followers aretransistors Q₃ and Q₄. The emitter followers isolate the ECL stage fromthe circuitry comprising the delay element.

The low-pass filter 16 comprises in FIG. 2 a resistor R₁ and the straycapacitance and input capacitance of comparator 27 represented b C_(s).The resistor R₁ is coupled to the emitter of transistor Q₃, as iscapacitor C₁ which is part of high-pass filter 18. Similarly, a resistorR₂ and the stray and input capacitances of comparator 27 compriseslow-pass filter 20. Resistor R₂ and capacitor C₂ are coupled to theemitter of transistor Q₄. Resistor R₂ and capacitor C₂ are of valuesequal to resistor R₁ and capacitor C₁, respectively. Capacitors C₁ andC₂ are chosen to restore the higher frequency components filtered by thecapacitance C_(s). In most circumstances the value of C₁ and C₂ will besimilar to that of C_(s).

Resistor R₁ is connected at its other end through summing node A to oneinput of the output stage comprising comparator 27, and resistor R₂ issimilarly connected at its other end through summing node B to the otherinput of the comparator. The high frequency paths containing capacitorsC₁ and C₂ connect at their other ends to the control element 24, whichin this embodiment comprises a current multiplier such as a conventionalGilbert gain cell that includes transistors Q₅ through Q₈ and diodes D₅and D₆. The current multiplier is adapted to direct a selectable portionof each higher frequency component passed by a high-pass filter to aidor oppose a lower frequency component passed by a low-pass filter. Thecollector of transistor Q₅ is coupled and the collector of transistor Q₇is cross coupled to resistor R₁ at node A. Symmetrically, the collectorof transistor Q₈ is coupled and the collector of transistor Q₆ is crosscoupled to the resistor R₂ at node B. Emitter coupled pairs oftransistors Q₅, Q₆ and Q₇, Q₈ are each biased by current sources 34 and36, respectively. The high frequency path of capacitor C₁ connects tothe coupled emitters of transistors Q₅ and Q₆. The path of capacitor C₂connects to the coupled emitters of transistors Q₇ and Q₈. The emittercoupled pairs are controlled by a pair of differential control currentsI_(S) +I_(c) and I_(S) -I_(c) from a differential source represented bybox 38, with I_(S) +I_(c) being directed to diode D₆ and to the base oftransistors Q₆ and Q₇ and I_(S) -I_(c) being directed to diode D₅ and tothe base of transistors Q₅ and Q₈. As taught by Gilbert, the currents inQ₅ and Q₆ (and also Q₈ and Q₇) are a ratio of the currents establishedin D₅ and D₆. The differential currents I_(S) +I_(c) and I_(S) -I_(c)oppose each other such that the transistors Q₆ and Q₇ are moreconductive than transistors Q₅ and Q₈ when +I_(c) exceeds -I_(c) andtransistors Q₆ and Q₇ are more conductive than transistors Q₅ and Q₈when -I_(c) exceeds +I_(c).

Operation of the delay element can now be understood with additionalreference to FIGS. 3 and 4. Assuming the negative-going transition of adigital signal is present at the..input terminal 30, FIG. 3 showsimmediately below the digital signal the waveform 40 of the lowerfrequency component passed by resistor R₁ and stray capacitance C_(s)and the waveform 42 passed by resistor R₂ and stray capacitance C_(s).Below waveforms 40, 42 are the waveforms 44 and 46 of the higherfrequency component passed by capacitors C₁ and C₂, respectively.Selectable portions of the higher frequency components can then bedirected through the high frequency paths to aid or oppose the lowerfrequency components to vary the delay of the output voltage. Because ofthe nature of the current multiplier, this delay is nearly a linearfunction of the control currents +I_(c) and -I_(c). At one extreme, thedelay is minimized by increasing -I_(c) so that transistors Q₅ and Q₈are fully on and transistors Q₆ and Q₇ are shut off. Referring again toFIG. 3, The higher frequency components in the form of currents passthrough transistors Q₅ and Q₈ to resistors R₁ and R₂ to aid the lowerfrequency components and reproduce substantially the original waveformof the digital signal as shown in dashed lines 48 and 50, therebydecreasing the delay. At the other extreme, delay is maximized byincreasing +I_(c) and decreasing -I_(c) such that transistors Q₆ and Q₇are fully on and transistors Q₅ and Q₆ are shut off. The higherfrequency components are now passed through the collectors oftransistors Q₆ and Q₇ and cross coupled to resistors R₁ and R₂ to opposethe lower frequency component, increasing the delay, as shown by dashedlines 52 and 54. When the control currents are equal, all transistors Q₅through Q₈ are on and the higher frequency component from each highfrequency path is split equally between nodes A and B, cancelling anyeffect on the lower frequency component.

FIG. 4 shows the differential voltages at the inputs to comparator 27.The figure indicates the median delay and its symmetrical nature for thepositive-going and negative-going transitions of the digital inputsignal. The differential voltages that comprise the digital signal arereconverted by the comparator 27 to a single-ended output signal withthe corresponding delay. Of course, differential outputs may be obtainedif desired. The comparator changes its output state at a threshold levelthat remains constant as the delay is varied because of theaforementioned symmetry at which the signals cross. FIG. 4 shows thethreshold level as a series of intersections between the twodifferential voltages.

The principles explained above may be suitably employed in asingle-ended version of the delay element as shown in FIG. 5, with likereference numerals retained for like components of FIG. 2. The in-phasevoltage is the only voltage utilized. The circuit functions like that inFIG. 2 except that the delay is now determined solely by the resistor R₁and the capacitance C_(s). No higher frequency component is crosscoupled to oppose the low frequency component. The higher frequencycomponent that passes through the capacitor C₁ may be added back to thelower frequency component through the collector of transistor Q₅ tominimize the delay or may be discarded altogether through the collectorof Q₆ to ground. Transistors Q₇ and Q₈ are used to maintain constantstanding current to resistor R₁ and transistor Q₃. The comparator 27 hasas its second input the reference voltage V_(REF) that sets thethreshold of the comparator midway between the high and low magnitudesof the voltage present at the input of the comparator. With reference toFIG. 3, the range of delay in this embodiment extends from the solidline 42 to the minimum delay represented by dashed line 50. FIG. 6 showsthe range of delay and that the symmetry is preserved in thepositive-going and negative-going transitions of the in-phase voltage sothat the delay is linearly related to the magnitude of the controlcurrents.

Having illustrated and described the principles of the invention inpreferred embodiments, it should be apparent to those skilled in the artthat the invention can be modified in arrangement and detail withoutdeparting from such principles. For example, the invention is by nomeans limited to ECL logic circuits. An amplifier with variablebandwidth, for example, can be formed by replacing the input and outputstages with linear amplifiers. I claim all modifications coming withinthe spirit and scope of the following claims.

I claim:
 1. An adjustable delay circuit for delaying passage of adigital signal, comprising:low-pass filter means for passing the lowerfrequency component of the digital signal, the lower frequency componenthaving a delay relative to the digital signal; high-pass filter means inparallel with the low-pass filter means for passing the higher frequencycomponent of the digital signal; control means for coupling a selectableportion of the higher frequency component to be summed with the lowerfrequency component to vary the delay produced by the lower frequencycomponent; and an output stage for receiving the lower frequencycomponent and selected portion of the of the higher frequency componentto reproduce the digital signal with the corresponding delay.
 2. Thedelay circuit of claim 1 in which the control means comprises a currentmultiplier that couples the high frequency component to the lowerfrequency component with which the higher frequency component is inphase in response to a control signal.
 3. The delay circuit of claim 1in which the low-pass filter means comprises a resistor and straycapacitance within the circuit and the high-pass filter means comprisesa capacitor adapted to pass the higher frequency component filtered bythe low-pass filter means.
 4. The adjustable delay circuit of claim 1 inwhich the control means is adapted to provide a delay in the digitalsignal symmetrical with respect to the positive-going and negative-goingtransitions thereof.
 5. A variable delay circuit for delaying passage ofa digital signal, comprising:an input stage for producing a pair ofoppositely phased differential output voltage signals representing thedigital signal; a pair of low-pass filters each receiving one of theoutput voltage signals from the input stage for passing the lowerfrequency component of the output voltage signals, each lower frequencycomponent having a delay relative to the output voltage signal; acurrent multiplier comprising two pairs of emitter-coupled transitors,the collector of one transistor of each pair coupled directly to theoutput of one low-pass filter and the collector of the other transistorof each pair cross coupled to the output of the other low-pass filter,the bases of the directly coupled transistor tied together and the basesof the cross-coupled transistors tied together; a pair of high-passfilters each having an input and an output, each input receiving one ofthe output voltage signals from the input stage and each output beingrespectively coupled to the emitters of each pair of emitter-coupledtransistors; means for providing a pair of differential currents, one tothe bases of the directly coupled transistors and one to the bases ofthe cross-coupled transistors, to couple a selectable portion of thehigher frequency component from each high-pass filter to be summed withthe lower frequency component from each low-pass filter to vary thedelay within the output voltage signals; and an output stage comprisinga comparator for comparing output voltage signals, each including thelower frequency component and the selectable portion of the higherfrequency component, and reproducing the digital signal withcorresponding delay as one output voltage signals exceeds the other andcauses the comparator to change state.
 6. An adjustable delay circuitfrom delaying passage of a digital signal, comprising:an emitterfollower for receiving the digital signal; a low-pass filter coupled tothe emitter of the emitter follower for passing the lower frequencycomponent of the digital signal to introduce a delay into the signal; ahigh-pass filter coupled to the emitter of the emitter follower inparallel with the low-pass filter for passing the high frequencycomponent of the digital signal; control means for biasing the emitterfollower with a constant current and for coupling a selectable portionof the high frequency component to be summed with the lower frequencycomponent; and an output stage for receiving the lower frequencycomponent and selected portion of the higher frequency component toreproduce the digital signal with the delay.